1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register for use as a scanning-line driving circuit for an image display apparatus or the like, which is formed by field effect transistors of the same conductivity type only.
2. Description of the Background Art
An image display apparatus (hereinafter referred to as a “display apparatus”) such as a liquid crystal display includes a display panel in which a plurality of pixels are arrayed in a matrix. A gate line (scanning line) is provided for each row of pixels (pixel line), and gate lines are sequentially selected and driven in a cycle of one horizontal period of a display signal, so that a displayed image is updated. As a gate-line driving circuit (scanning-line driving circuit) for sequentially selecting and driving pixel lines, i.e., gate lines, a shift register for performing a shift operation in one frame period of a display signal can be used.
To reduce the number of steps in the manufacturing process of a display apparatus, such shift register used as the gate-line driving circuit is preferably formed by field effect transistors of the same conductivity type only. Accordingly, various types of shift registers formed by N- or P-type field effect transistors only and display apparatuses containing such shift registers have been proposed (e.g., U.S. Pat. No. 5,222,082, and Japanese Patent Application Laid-Open Nos. 2002-313093, 2002-197885 and 2004-103226). As a field effect transistor, a metal oxide semiconductor (MOS) transistor, a thin film transistor (TFT), or the like is used.
A conventional shift register has a problem caused by a leakage current at a node (specifically, nodes P1 and P2 shown in FIG. 2 of the above-mentioned U.S. Pat. No. 5,222,082) to which a gate electrode of a transistor of an output stage is connected.
For instance, when a leakage current occurs at a gate electrode node (P1) of a transistor connected between an output terminal of a shift register and a clock terminal defining an output signal output from the output terminal, an impedance of the transistor when discharge takes place at the output terminal increases, and the time required for the discharge thus increases. Therefore, the fall time of the output signal increases, causing the output signal to be unable to follow a clock signal input to the clock terminal. As a result, an increased fall time of the output signal in the gate-line driving circuit of a display apparatus causes a problem in that a plurality of gate lines are driven at the same time, resulting in failure to achieve a normal display (which will be described later in detail).
Further, when a leakage current occurs at a gate electrode node (P2) of a transistor connected between the output terminal and a reference voltage terminal of the shift register, an impedance of the transistor in the on state (conducting state) increases. That is, an output impedance of the shift register increases, arising a concern that the potential at the output terminal may become unstable. In the case where the output signal from the gate-line driving circuit thus becomes unstable, the problem of failure to achieve a normal display also arises (which will be described later in detail).
A shift register described in the above-mentioned JP2002-313093 includes inversion-preventing circuits (transistors T7, T8) connected to the gate electrode node (n2) of an NMOS transistor (transistor T2) connected between an output terminal and a power source for stabilizing the potential at the node. The NMOS transistor needs to be held off (cutoff state) in a period during which an output line is in low level. The inversion-preventing circuits prevent the NMOS transistor from unnecessarily turning on due to level transition of the output line during the period in which the output line is in the low level, which solves another problem different from the above-described one.